drm/apple: support interchange compression

Signed-off-by: Oliver Bestmann <oliver.bestmann@googlemail.com>

Author: oliverbestmann

drivers/gpu/drm/apple/iomfb_plane.h

@@ -67,7 +67,26 @@ struct dcp_plane_info {
 	u16 tile_size;
 	u8 tile_w;
 	u8 tile_h;
-	u32 unk[13];
+	u8 unk1[0xd];
+	u8 address_format;
+	u8 unk2[0x26];
+} __packed;
+
+struct dcp_compression_info {
+	u32 tile_w;
+	u32 tile_h;
+	u32 meta_offset;
+	u32 data_offset;
+	u32 tile_meta_bytes;
+	u32 tiles_w;
+	u32 tiles_h;
+	u32 unk1;
+	u32 compresson_type;
+	u32 unk3;
+	u8 _pad1[3];
+	u32 tile_bytes;
+	u32 row_stride;
+	u8 pad2;
 } __packed;
 
 struct dcp_component_types {
@@ -100,7 +119,7 @@ struct dcp_surface {
 	u64 has_comp;
 	struct dcp_plane_info planes[DCP_SURF_MAX_PLANES];
 	u64 has_planes;
-	u32 compression_info[DCP_SURF_MAX_PLANES][13];
+	struct dcp_compression_info compression_info[DCP_SURF_MAX_PLANES];
 	u64 has_compr_info;
 	u32 unk_num;
 	u32 unk_denom;

drivers/gpu/drm/apple/plane.c

@@ -7,6 +7,9 @@
 
 #include "iomfb_internal.h"
 
+#include "iomfb_plane.h"
+#include "linux/printk.h"
+#include "vdso/align.h"
 #include <drm/drm_atomic.h>
 #include <drm/drm_atomic_helper.h>
 #include <drm/drm_fourcc.h>
@@ -257,8 +260,12 @@ static void apple_plane_atomic_update(struct drm_plane *plane,
 		.pel_h = 1,
 		.has_comp = 1,
 		.has_planes = 1,
+		.has_compr_info = 1,
 	};
 
+	BUILD_BUG_ON(sizeof(struct dcp_plane_info) != 0x50);
+	BUILD_BUG_ON(sizeof(struct dcp_compression_info) != 0x34);
+
 	/* Populate plane information for planar formats */
 	struct dcp_surface *surf = &new_state->surf;
 	for (int i = 0; fb->format->num_planes && i < fb->format->num_planes; i++) {
@@ -279,6 +286,35 @@ static void apple_plane_atomic_update(struct drm_plane *plane,
 			.tile_h = bh,
 		};
 
+		pr_info("dcp: plane %d modifiers: %llx", i, fb->modifier);
+
+		if (fb->modifier == DRM_FORMAT_MOD_APPLE_INTERCHANGE_COMPRESSED) {
+			// pr_info("dcp: got framebuffer with XCHG modifier, enable compression");
+
+			u32 tw = ALIGN(width, 16) / 16;
+			u32 th = ALIGN(height, 16) / 16;
+			u32 tsize_B = 16 * 16 * 4;
+
+			surf->planes[i].tile_w = 16;
+			surf->planes[i].tile_h = 16;
+			surf->planes[i].stride =  tw * tsize_B;
+			surf->planes[i].tile_size = tsize_B;
+			surf->planes[i].address_format = 5; // interchange tiles
+
+			surf->compression_info[i] = (struct dcp_compression_info) {
+				.tile_w = 16,
+				.tile_h = 16,
+				.data_offset = 0,
+				.meta_offset = ALIGN(tw * th * tsize_B, 128),
+				.tile_meta_bytes = 8,
+				.tiles_w = tw,
+				.tiles_h = th,
+				.tile_bytes =  tsize_B,
+				.row_stride = tw * tsize_B,
+				.compresson_type = 3, // interchange compression
+			};
+		}
+
 		if (i > 0)
 			surf->buf_size += surf->planes[i].size;
 	}
@@ -426,6 +462,7 @@ static const u32 dcp_overlay_formats_12_x[] = {
 };
 
 u64 apple_format_modifiers[] = {
+	DRM_FORMAT_MOD_APPLE_INTERCHANGE_COMPRESSED,
 	DRM_FORMAT_MOD_LINEAR,
 	DRM_FORMAT_MOD_INVALID
 };

include/uapi/drm/drm_fourcc.h

@@ -1599,6 +1599,7 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
  */
 #define DRM_FORMAT_MOD_APPLE_GPU_TILED fourcc_mod_code(APPLE, 1)
 #define DRM_FORMAT_MOD_APPLE_GPU_TILED_COMPRESSED fourcc_mod_code(APPLE, 2)
+#define DRM_FORMAT_MOD_APPLE_INTERCHANGE_COMPRESSED fourcc_mod_code(APPLE, 3)
 
 /*
  * AMD modifiers