feat: Intel GPU Max (Ponte Vecchio) OpenMP target offload support#1445
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sbryngelson wants to merge 34 commits into
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feat: Intel GPU Max (Ponte Vecchio) OpenMP target offload support#1445sbryngelson wants to merge 34 commits into
sbryngelson wants to merge 34 commits into
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- Fix INTEL_COMPILER_ID Fypp variable: 'Intel' -> 'IntelLLVM' in
shared_parallel_macros.fpp and omp_macros.fpp so Intel-specific
OMP macro branches actually match for ifx builds
- Add Intel-specific OMP directives in omp_macros.fpp:
target teams loop (no bind/defaultmap clauses ifx rejects),
OMP_MKL_DISPATCH() emitting ! dispatch for oneMKL GPU FFT
- Add GPU_MKL_DISPATCH() in parallel_macros.fpp for oneMKL DFTI
dispatch from device-mapped allocatables (Intel GPU FFT path)
- CMakeLists.txt:
- Fix Intel compiler ID checks: 'Intel' -> 'IntelLLVM'
- Switch -fopenmp to -fiopenmp -fopenmp-targets=spir64 for ifx
- Add -fpp to global IntelLLVM compile options
- Compile mkl_dfti_omp_offload.f90 via add_custom_command with
minimal flags (no -free -fpp) to avoid OpenMP 5.2 clause issues
- Link -qmkl=parallel, libmkl_sycl_dft, libsycl, libOpenCL for
Intel GPU FFT backend
- Skip building FFTW from source for IntelLLVM (uses oneMKL)
- m_fftw.fpp: Add Intel GPU path using oneMKL DFTI + ! dispatch
for azimuthal Fourier filter; CPU path still uses FFTW for Intel
- m_pressure_relaxation.fpp: Fix ifx SPIR64 bug -- change
dimension(sys_size) -> dimension(:) in all declare-target helper
interfaces to avoid llvm-spirv InvalidArraySize (SPIR-V requires
compile-time constant array bounds; sys_size is a runtime value)
- m_compute_levelset.fpp: Guard GPU_PARALLEL_LOOP with Fypp
MFC_COMPILER != INTEL_COMPILER_ID for s_apply_levelset; ifx
if-else dispatch to multiple declare-target routines in a target
teams loop triggers LLVM dominance error, and the dispatch-wrapper
fix triggers an ifx ICE -- host fallback is the only workaround
- docs/documentation/intel-gpu-max.md: Document build environment,
required library paths, known ifx bugs, and GPU device access
Tested on GT CRNCH RoboGator (dash3):
ifx 2025.3.3, oneMKL 2026.0, Intel Data Center GPU Max 1100
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…-inline) The LLVM inliner at O1+ pulls declare-target(seq) geometry routines into target-teams-loop kernels, generating LLVM IR that crashes llvm-spirv. Two complementary fixes: 1. Split s_apply_levelset into one GPU_PARALLEL_LOOP per geometry type so each kernel calls exactly one declare-target routine (also avoids the multi-callee phi-node dominance error from the original dispatch). 2. Add per-file -fno-inline in CMakeLists for IntelLLVM+OpenMP builds so the inliner cannot pull device routines into the kernel body. Verified: compiles at O3 -fno-inline on ifx 2025.3.3 + SPIR64. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
Verified: m_thermochem.f90 (pyrometheus-generated, 10 species / 29 reactions) and m_chemistry.fpp both compile at O3 + SPIR64 without ICE on ifx 2025.3.3. 1D_reactive_shocktube case runs to completion with CPU fallback. Documents the benign ifx warning #8694 about declare-target visibility across module boundaries, and the build/run workflow for chemistry cases. Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
…r OpenMP device routines
…chio) Two root causes of ZE_RESULT_ERROR_MODULE_LINK_FAILURE at runtime on Intel GPU Max 1100 (Ponte Vecchio) with OpenMP target offload (--gpu mp): 1. mkl_dfti_omp_offload.o SPIR-V import problem: MKL's mkl_dfti_omp_offload.f90 compiled with -fopenmp-targets=spir64 produces SPIR-V with Import declarations for MKL SYCL DFT functions (mkl_dfti_compute_forward_dz_omp_offload, etc.) that the OpenMP Level Zero plugin cannot resolve at zeModuleDynamicLink time. Fix: Use clang-offload-bundler to strip the SPIR-V device bundle from mkl_dfti_omp_offload.o, linking only host code. The MKL DFTI interface module (.modmic) is still compiled for use by dependent translation units, but ! dispatch for DFT calls falls back to CPU execution. 2. m_thermochem.f90 empty SPIR-V problem (chemistry/pyrometheus): Pyrometheus generates '#define GPU_ROUTINE(name) ! declare target' (a C macro). When ifx processes the file with -free -fpp, the Intel Fortran preprocessor strips '! declare target' after C macro expansion because '!' is treated as a Fortran comment character after expansion, leaving an empty SPIR-V bundle with no exported device symbols. Fix: Post-process generated m_thermochem.f90 to remove the #define macro and replace GPU_ROUTINE(name) call sites with literal '! declare target' directives, which are visible to the Fortran front-end. Verified: 1D advection case runs to completion on Intel GPU Max 1100 with OMP_TARGET_OFFLOAD=MANDATORY and 'Simulating ... with OpenMP offloading.'
Automatically set Intel Level Zero environment variables when running with --gpu mp and ifx compiler: - LIBOMPTARGET_LEVEL_ZERO_COMMAND_BATCH=256: batch up to 256 Level Zero commands before flushing, reducing host-GPU synchronization overhead. Measured ~9% throughput improvement on Intel GPU Max 1100 (PVC). - SYCL_PI_LEVEL_ZERO_TRACK_INDIRECT_ACCESS_MEMORY=0: disable per-kernel indirect access tracking (zeMemGetAllocProperties, ~2100 calls/step). Safe because MFC manages all GPU allocations via @:ALLOCATE/@:DEALLOCATE and scalar_field pointers are never aliased with host memory. When --fastmath is also requested: - LIBOMPTARGET_LEVEL_ZERO_COMPILATION_OPTIONS=-cl-fast-relaxed-math: enables GPU JIT fast-math (fused MAD, fast transcendentals, finite- math-only). Equivalent to nvfortran -gpu=fastmath for OpenACC builds.
The IntelLLVM branch inadvertently dropped the Intel (ifort) elseif, leaving classic ifort CPU builds without the -free flag. Add it back as a separate branch so ifort and ifx coexist correctly.
Adds source ./mfc.sh load -c crnch -m g support for the GT CRNCH RoboGator nodes with Intel GPU Max 1100 (Ponte Vecchio). Sets FC, PATH, MKLROOT, LD_LIBRARY_PATH, and LIBRARY_PATH for oneAPI 2025.1 at the fixed install path (no Lmod modules available for 2025.1). Also fixes modules.sh to skip 'module load' when the module list is empty, supporting systems that configure entirely via env var exports.
When FC is an MPI wrapper (mpiifx), CMAKE_Fortran_COMPILER parent dir points to the MPI bin dir, not the compiler bin dir. clang- offload-bundler lives in compiler/bin/compiler/ which is only reachable via the real ifx location. Resolve ifx from PATH first.
- Add -DCMAKE_POSITION_INDEPENDENT_CODE=ON to LAPACK ExternalProject so ifx-compiled Fortran objects link correctly on PIE-default systems (Ubuntu 22.04+) - Update crnch module to use mpiifx as FC and add Intel MPI 2021.14 to PATH, LD_LIBRARY_PATH, LIBRARY_PATH, and I_MPI_ROOT for MPI-enabled builds
Ubuntu 22.04 GCC defaults to --enable-default-pie, causing the LAPACK FortranCInterface compatibility test to fail when linking ifx-compiled Fortran objects into a PIE executable. Fix by: - Adding -DCMAKE_EXE_LINKER_FLAGS=-no-pie to suppress PIE for LAPACK test executables (LAPACK itself is a static library so PIE is irrelevant) - Passing CMAKE_Fortran_COMPILER explicitly so LAPACK uses the same ifx/mpiifx that MFC uses rather than whatever cmake auto-detects
…lLLVM FFTW is a pure C library; the Fortran compiler ID is irrelevant to building it. The IntelLLVM exception was unnecessarily preventing FFTW from being built from source when using ifx/mpiifx, causing post_process tests that require FFTW to fail on systems without a system-provided double-precision FFTW.
Without this, Intel MPI's OFI transport fails to initialize on dash4 (no InfiniBand/OmniPath) with 'Unknown error class' in MPIDI_OFI_mpi_init_hook. Setting I_MPI_FABRICS=shm forces shared-memory transport for intra-node communication, which works correctly for single-node GPU runs.
Add end-to-end support for building and running MFC on Intel Data Center GPU Max (Ponte Vecchio) using ifx 2025.0+ with OpenMP target offload to SPIR-V/SPIR64. Verified on GT CRNCH RoboGator (dash4) with Intel GPU Max 1100. All 161 1D regression tests pass. ## Compiler and build system - Recognize IntelLLVM compiler ID throughout CMakeLists.txt (was Intel) - Add -fiopenmp -fopenmp-targets=spir64 compile/link flags for GPU builds - Add -fp-model=precise to prevent ifx FP reassociation in SPIR-V kernels - Add -fpp to global compile flags for Intel preprocessor compatibility - Link MKL parallel, libmkl_sycl_dft, libsycl, libOpenCL for oneMKL FFT - Strip SPIR-V from mkl_dfti_omp_offload.o via clang-offload-bundler to fix zeModuleDynamicLink Level Zero failures - Add --intel-aot flag: AOT compilation via ocloc to native PVC ISA, eliminates ~30 min Level Zero JIT delay (test runs: 30 min -> 14 sec) - Add IntelLLVM to no-FFTW-from-source list in dependencies/CMakeLists.txt - Fix LAPACK PIE link error with ifx on Ubuntu 22.04 ## GPU kernel fixes - omp_macros.fpp: add Intel-specific OMP_PARALLEL_LOOP, END_OMP_PARALLEL_LOOP, OMP_ROUTINE, OMP_MKL_DISPATCH branches for SPIR-V codegen - parallel_macros.fpp: add GPU_MKL_DISPATCH() macro for oneMKL dispatch - shared_parallel_macros.fpp: add USING_INTEL Fypp variable; extend all #:if not MFC_CASE_OPTIMIZATION and USING_AMD guards to include USING_INTEL and bare #:if USING_AMD guards for dimension(sys_size) in m_cbc/m_compute_cbc - m_fftw.fpp: oneMKL DFTI + ! dispatch GPU FFT path for Intel - m_compute_levelset.fpp: split single if-else dispatch to fix multi-callee phi-node issue and inliner ICE; add -fno-inline workaround - m_riemann_solvers.fpp, m_variables_conversion.fpp, m_bubbles_EE.fpp, m_weno.fpp, m_sim_helpers.fpp, m_pressure_relaxation.fpp, m_boundary_common, m_chemistry.fpp, m_phase_change.fpp, m_bubbles_EL.fpp, m_viscous.fpp, m_ibm.fpp, m_hyperelastic.fpp, m_acoustic_src.fpp, m_surface_tension.fpp, m_data_output.fpp, m_qbmm.fpp, m_compute_cbc.fpp, m_cbc.fpp, m_ib_patches.fpp: explicit array sizes in GPU_ROUTINE arguments (no assumed-shape in SPIR-V) and extend VLA guards to USING_INTEL for non-case-optimized GPU builds - m_helper.fpp: Intel-specific workarounds for SPIR-V codegen ## Toolchain - Add GT CRNCH RoboGator (crnch) module entry with Intel oneAPI 2025.1 - run.py: Intel GPU detection, set LIBOMPTARGET_LEVEL_ZERO_COMMAND_BATCH=256 and SYCL_PI_LEVEL_ZERO_TRACK_INDIRECT_ACCESS_MEMORY=0 for ~16% speedup - run/input.py: post-process pyrometheus m_thermochem.f90 for --gpu mp (replace C-macro GPU_ROUTINE with literal ! declare target) - build.py, state.py: --intel-aot flag and ocloc device selection - test.py: --binary mpirun support to bypass SLURM srun slot limits on CRNCH - bootstrap/modules.sh: crnch module bootstrap - templates/include/helpers.mako: Intel MPI I_MPI_FABRICS=shm hint - modules: crnch entry (Intel oneAPI 2025.1, mpiifx, GPU Max 1100) ## Documentation - docs/documentation/intel-gpu-max.md: full build, run, troubleshoot guide
Claude Code ReviewHead SHA: 6b1d0de Files changed:
Findings: Banned integer kind literals in
|
…n m_qbmm and m_hyperelastic
…bric removed in 2021.x)
…nd OFI provider requirements
… permission issue
…ulti-node MPI docs
…l GPU build
Add TAMU HPRC ACES (Intel GPU Max 1100/Ponte Vecchio) cluster entry with
iimpi/2023b + imkl/2023.2.0 modules. Fix three CMake issues needed for the
ifx SPIR-V GPU build:
1. clang-offload-bundler: add bin-llvm/ hint (Intel 2023.x path)
2. MKL SYCL DFT lib: add mkl_sycl fallback name and lib/intel64 hint for
MKL < 2024 which ships a monolithic mkl_sycl.so instead of mkl_sycl_dft.so
3. ifx 2023.2 SPIR-V backend ICEs: two root causes hit during compilation:
(a) error #5623 - module-level ! declare target derived-type arrays
with pointer members accessed via inner sequential loop indices inside
target regions generate invalid LLVM IR (dominance violation)
(b) errors #5623/#5633 - complex GPU kernels with ghost_point /
ib_patch_parameters struct mapping + declare target (seq) routines
crash the SPIR-V lowering pass
Workaround: -UMFC_OpenMP per-source flag suppresses #ifdef MFC_OpenMP
target directives so m_ib_patches, m_surface_tension, m_igr, and
m_compute_levelset compile CPU-only (all are init or specialized solvers
called from CPU context, not the hot-path fluid solver kernels).
m_rhs and m_time_steppers use -O0 to attempt to preserve GPU offload.
…mpiles clean Direct compilation tests on PVC node confirmed that m_rhs.fpp.f90 and m_time_steppers.fpp.f90 both compile without ICE at -O3. The -O0 fallback was applied preemptively based on code-pattern analysis but was never actually needed — the build had been blocked by the four CPU-fallback files (m_ib_patches, m_surface_tension, m_igr, m_compute_levelset), and once those were fixed the hot-path GPU kernels compiled at full optimization. All simulation GPU kernels now compile at -O3 with no per-file flag hacks.
…IR-V ICE workarounds
…ule hierarchy requires these versions)
… to avoid SPIR-V #5633 ICE
m_ice_min.f90: 60-line minimum reproducer - matmul() inside ! declare target sub called from ! target teams loop - ICEs at O1/O2/O3; passes with -fno-inline - manual loops (no matmul intrinsic) compile fine, confirming matmul is trigger m_ice_repro.f90: structured reproducer matching real MFC m_compute_levelset - derived-type struct, allocatable module arrays, 10 separate target loops - same ICE pattern; confirms -fno-inline per-file workaround Bisection scripts (run_cl5b.sh, run_cl5c.sh) document the investigation: char field, interp_coeffs, loop count all ruled out matmul with struct-member or local matrix confirmed as trigger
…e -fno-inline workaround The matmul() intrinsic inside ! declare target subroutines triggers ifx 2025.1.1 SPIR-V ICE #5633 when the subroutine is inlined into a target teams loop kernel. Manual 3x3 matvec (f_mv3) avoids the intrinsic entirely, allowing the GPU code path to compile at all opt levels without the -fno-inline workaround in CMakeLists.txt.
…nk step ocloc runs at link time and requires significantly more than SLURM's 1G default. 32G is sufficient; nodes have 500G available. Also bumped time limit to 90min for the longer ocloc pass.
…pilation The --intel-aot flag was previously only passed to CMake cache but never used by CMakeLists.txt -- all IntelLLVM OpenMP builds used hardcoded spir64 (JIT) regardless. This caused zeModuleCreate failures at runtime since the Level Zero driver could not JIT-compile the embedded SPIR-V. Add option() declaration for MFC_Intel_AOT and MFC_Intel_AOT_DEVICE, then branch on MFC_Intel_AOT in the IntelLLVM+OpenMP section to use spir64_gen + ocloc AOT compilation when enabled. The SHELL: prefix preserves shell quoting for the -Xopenmp-target-backend argument (-device pvc) passed through to ocloc at link time.
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Summary
Adds end-to-end support for building and running MFC on Intel Data Center GPU Max 1100 (Ponte Vecchio) using
ifx 2025.0+with OpenMP target offload to SPIR-V/SPIR64. Verified on GT CRNCH RoboGator (dash4). All 161 1D regression tests pass on the Intel GPU.Usage
Changes
Build system (
CMakeLists.txt,toolchain/)IntelLLVMcompiler ID throughout (wasIntel)-fiopenmp -fopenmp-targets=spir64compile/link flags for GPU builds-fp-model=preciseto prevent ifx FP reassociation in SPIR-V kernels--intel-aotflag: AOT compilation viaoclocto native PVC ISA, eliminates ~30 min Level Zero JIT delay (test runs: 30 min → 14 sec)mkl_dfti_omp_offload.oviaclang-offload-bundlerto fixzeModuleDynamicLinkLevel Zero failureslibmkl_sycl_dft,libsycl,libOpenCLfor oneMKL FFTcrnch) module entry with Intel oneAPI 2025.1run.py: auto-setLIBOMPTARGET_LEVEL_ZERO_COMMAND_BATCH=256andSYCL_PI_LEVEL_ZERO_TRACK_INDIRECT_ACCESS_MEMORY=0(~16% throughput gain)m_thermochem.f90for--gpu mp: replace C-macroGPU_ROUTINEwith literal!$omp declare targettest.py:--binary mpirunsupport to bypass SLURMsrunslot limits on CRNCHGPU macro layer (
src/common/include/)omp_macros.fpp: Intel-specificOMP_PARALLEL_LOOP,OMP_ROUTINE,OMP_MKL_DISPATCHbranches for SPIR-V codegenparallel_macros.fpp:GPU_MKL_DISPATCH()macro for oneMKL dispatchshared_parallel_macros.fpp: addUSING_INTELFypp variable; extend all#:if not MFC_CASE_OPTIMIZATION and USING_AMDguards to(USING_AMD or USING_INTEL), and bare#:if USING_AMDguards fordimension(sys_size)in CBC modulesSource fixes (Intel SPIR-V constraints)
num_fluids_max,dim(3), etc.) across 20 filesUSING_AMDVLA guards toUSING_INTELinm_riemann_solvers,m_variables_conversion,m_bubbles_EE,m_weno,m_cbc,m_compute_cbc, and 13 other filesm_fftw.fpp: oneMKL DFTI +!$omp dispatchGPU FFT path for Intelm_compute_levelset.fpp: split single if-else dispatch to fix multi-callee phi-node issue andifxinliner ICEDocumentation
docs/documentation/intel-gpu-max.md: full build, run, and troubleshooting guide for Intel GPU MaxTest plan
dash4)