[CIR][CIRGen] Handle AS on function return allocas for heterogeneous languages

[RiverDave]

Currently, one gap in AS handling between CIR and OG is the fact that return values are casted to their default stack addresses in some heterogeneous targets like AMDGPU. see:

OG:

define dso_local void @_Z5test4Pi(ptr noundef %a) #0 {
entry:
  %a.addr = alloca ptr, align 8, addrspace(5)
  %a.addr.ascast = addrspacecast ptr addrspace(5) %a.addr to ptr
...

This PR aims for further parity in address space handling for return value allocas on AMDGPU targets (& others..) and updates test patterns to handle alignment attributes in CIR.

• Modified emitAndUpdateRetAlloca in to use CreateMemTemp instead of emitAlloca, ensuring the return value alloca gets the proper address space cast on AMDGPU (addrspace 5 → flat).

• Updated stores/loads to __retval to go through ReturnValue (the cast address) instead of FnRetAlloca (raw alloca). This is essentially what OG does, see:

  clangir/clang/lib/CodeGen/CGStmt.cpp

  Line 1700 in 5237bd4

  EmitStoreOfScalar(Ret, MakeAddrLValue(ReturnValue, RV->getType()),

  . Indirectly, this implies that loads and stores now hold alignment information at the CIR level. I adjusted the tests to make them compliant with this.

[RiverDave]

Warning

This pull request is not mergeable via GitHub because a downstack PR is open. Once all requirements are satisfied, merge this PR as a stack on Graphite.
Learn more

• [CIR][CIRGen] Emit Address Spaces on RTTI globals #2093
• [CIR][CIRGen] Handle AS on function return allocas for heterogeneous languages #2090 👈 (View in Graphite)
• [CIR][CIRGen] Handle AS in temp Allocas and override AS methods for AMDGPU #2088
• main

This stack of pull requests is managed by Graphite. Learn more about stacking.

[bcardosolopes]

LGTM